This invention relates to a flip-flop circuit arrangement which well adapted for use as a peripheral circuit, for example as a decoder circuit, particularly of the NOR type, an inverter for address inputs, and a sense amplifier, for a semiconductor memory.
A NOR decoder circuit has been employed as a circuit for decoding a group of address signals for a memory circuit comprising a large number of insulated-gate field-effect transistors. A conventional NOR decoder circuit comprises an output terminal connected to predetermined ones of the memory cells through an address line driver. The NOR decoder circuit further comprises a load field-effect transistor having a source electrode connected to the output terminal, a drain electrode supplied with d.c. power, and an insulated gate electrode supplied with a precharge signal. The NOR decoder circuit still further comprises a plurality of decoder field-effect transistors, equal in number to the input address signals to be decoded, having grounded source electrodes, drain electrodes connected to the output terminal, and insulated gate electrodes supplied with the respective true and/or complementary address signals. The precharge signal makes the decoder circuit produce a logic "1" level output signal at the circuit output terminal when no address signals are supplied to the decoder transistors. When at least one of the true and/or complementary address signals applied to the decoder transistors is at the logic "1" level, the decoder output signal is switched to a logic "0" level and thus put in a nonselecting state. Only when all of the true and/or complementary address signals applied to the decoder transistors are logic "0's", the decoder output signal remains at the logic "1" level and is thus in a selecting state.
For input address signal, N in number, use is made of 2.sup.N similar decoder circuits. In response to a group of input address signals, only one of the decoder circuits derives the selecting decoder output signal while others produce nonselecting decoder output signals. The address line drivers are activated after all nonselecting decoder output signals are switched to the logic "0" level.
In addition to its simple structure, the NOR decoder circuit is advantageous by reason of its low power consumption. Power is needed only for switching the precharged logic "1" level to the nonselecting logic "0" level. No d.c. power is consumed. On the other hand, access time depends on the time required to switch the precharged logic "1" level to the nonselecting logic "0" level. It is therefore necessary in order to reduce access time to raise the current sinking capability of the decoder transistors and to hence increase the geometrical dimensions thereof. In an integrated circuit, this means that the decoder transistors occupy an objectionably wide area.
Therefore, it is required that the decoder circuit can operate at a high speed without occupying a wide area in the integrated circuit device. Moreover, a similar requirement is present in other circuits, such as a sense amplifier, an address inverter used in a memory circuit, and the like. It has been found that this requirement can be met by providing an additional high-speed flip-flop type circuit for the circuit to operate at high speed.